Self-aligned, low-ressistance, efficient memory array

ABSTRACT

The present invention seeks to reduce the amount of current required for a write operation by using a process for forming the read conductor within a recessed write conductor, the write conductor itself formed within a trench of an insulating layer. The present invention protects the MTJ from the voltages created by the write conductor by isolating the write conductor and enabling the reduction of current necessary to write a bit of information.

FIELD OF THE INVENTION

The present invention relates generally to magnetoresistive randomaccess memory (MRAM), and more specifically, to read and writeconductors for MRAM.

BACKGROUND OF THE INVENTION

Integrated circuit designers have always sought the ideal semiconductormemory: a device that is randomly accessible; can be written to or readfrom very quickly; is non-volatile, but indefinitely alterable; andconsumes little power. Magnetoresistive random access memory (MRAM)technology has been increasingly viewed as offering all of theseadvantages.

An MRAM memory cell contains a non-magnetic conductor forming a lowerelectrical contact, a pinned magnetic layer, a barrier layer, a freemagnetic layer, and a second non-magnetic conductor. The pinned magneticlayer, tunnel barrier layer, and free magnetic layer are collectivelytermed the magnetic tunnel junction (MTJ) element.

Information can be written to and read from the MRAM cell as a “1” or a“0,” where a “1” generally corresponds to a high resistance level, and a“0” generally corresponds to a low resistance level. Directions ofmagnetic orientations in the magnetic layers of the MRAM cell causeresistance variations. Magnetic orientation in one magnetic layer ismagnetically fixed or pinned, while the magnetic orientation of theother magnetic layer is variable so that the magnetic orientation isfree to switch direction. In response to the shifting state of the freemagnetic layer, the MRAM cell exhibits one of two different resistancesor potentials, which, as described above, are read by the memory circuitas either a “1” or a “0.” It is the creation and detection of these twodistinct resistances or potentials that allows the memory circuit toread from and write information to an MRAM cell.

A bit of information may be written into the MTJ element of an MRAM cellby applying orthogonal magnetic fields directed within the XY-plane ofthe MTJ element. Depending on the strength of the magnetic fields, whichare created by a current passing through the write line, the freemagnetic layer's polarization may remain the same or switch direction.The free magnetic layer's polarization then may continue to be parallelto the pinned magnetic layer's polarization, or anti-parallel to thepinned magnetic layer's polarization.

A bit of information is retrieved from the MTJ element by measuring itsresistance via a read current directed along the Z-axis, transverse tothe XY-plane. The state of the MTJ element can be determined by the readconductor measuring the resistance of the memory cell. The MTJ elementis in a state of low resistance if the overall orientation ofmagnetization in the free magnetic layer is parallel to the orientationof magnetization of the pinned magnetic layer. Conversely, the MTJelement is in a state of high resistance if the overall orientation ofmagnetization in the free magnetic layer is anti-parallel to theorientation of magnetization in the pinned magnetic layer.

Conventional MRAM structures, such as that depicted in FIG. 1, typicallyhave a write conductor 20 and a read conductor 26, separated by a liner17, together forming a word line 32. Other layers may be included, butare omitted for clarity. The word line 32 of a conventional MRAMstructure is typically formed in a first insulating layer (typically anoxide layer) 10, with an MTJ element 28 formed over the word line 32.Typically, the read conductor 26 is less than 500 nm wide and less than50 nm thick. The dimensions of the read conductor 26 and the liner 17separate the MTJ element 28 from the write conductor 20.

Conventional MRAM structures electrically isolate the write conductor 20from the MTJ element 28 to protect the MTJ element 28 from a voltagecreated when a current is applied to the write conductor 20 to write abit of information onto the MTJ element 28. However, by isolating thewrite conductor 20 from the MTJ element 28, a higher current isnecessary to achieve the same electromagnetic field to write a bit ofinformation if the write conductor 20 was not electrically isolated. Thehigher current results in higher voltages applied to the MTJ element 28.

BRIEF SUMMARY OF THE INVENTION

The present invention seeks to reduce the amount of current required fora write operation by using a process for forming the read conductorwithin a recessed write conductor, the write conductor itself formedwithin a trench of an insulating layer. The present invention protectsthe MTJ from the voltages created by the write conductor by isolatingthe write conductor and enabling the reduction of current necessary towrite a bit of information.

BRIEF DESCRIPTION OF THE DRAWINGS

The above-described features and advantages of the invention will bemore clearly understood from the following detailed description, whichis provided with reference to the accompanying drawings in which:

FIG. 1 depicts a conventional MRAM cell structure.

FIG. 2 depicts a stage of processing of an MRAM device, in accordancewith an exemplary embodiment of the invention;

FIG. 3 depicts a further stage of processing of the FIG. 2 MRAM device;

FIG. 4 depicts a further stage of processing of the FIG. 3 MRAM device;

FIG. 5 depicts a further stage of processing of the FIG. 4 MRAM device;

FIG. 6 depicts a further stage of processing of the FIG. 5 MRAM device;

FIG. 7 depicts a further stage of processing of the FIG. 6 MRAM device;

FIG. 8 depicts a further stage of processing of the FIG. 7 MRAM device;

FIG. 9 depicts a further stage of processing of the FIG. 8 MRAM device;

FIG. 10 depicts a further stage of processing of the FIG. 9 MRAM device;

FIG. 11 depicts a further stage of processing of the FIG. 10 MRAMdevice;

FIG. 12 depicts a further stage of processing of the FIG. 11 MRAMdevice;

FIG. 13 depicts a further stage of processing of the FIG. 12 MRAMdevice;

FIG. 14 depicts a further stage of processing of the FIG. 13 MRAMdevice;

FIG. 15 depicts a further stage of processing of the FIG. 14 MRAMdevice;

FIG. 16 depicts a further stage of processing of the FIG. 15 MRAMdevice;

FIG. 17 is a cutaway perspective view of a semiconductor chip containinga plurality of MRAM devices according to an exemplary embodiment of theinvention; and

FIG. 18 is a schematic diagram of a processor system incorporating anMRAM device in accordance with an exemplary embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description, reference is made to specificexemplary embodiments of the invention. It is to be understood thatother embodiments may be employed, and that structural and electricalchanges may be made without departing from the spirit or scope of thepresent invention.

The term “semiconductor substrate” is to be understood to include anysemiconductor-based structure that has an exposed semiconductor surface.The semiconductor structure should be understood to include silicon,silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Thesemiconductor substrate need not be silicon-based. The semiconductorcould be silicon-germanium, germanium, or gallium arsenide. Whenreference is made to a semiconductor substrate in the followingdescription, previous process steps may have been utilized to formregions or junctions in or over the base semiconductor or foundation.Also, the invention may be formed over non-semiconductor substrates.

The steps below are discussed as being performed in an exemplary order,however this order may be altered and still maintain the spirit andscope of the invention.

Referring now to the drawings, where like elements are designated bylike reference numerals, FIG. 2 depicts a cross-section of an MRAMmemory cell during an intermediate stage of processing, wherein a firstinsulating layer (preferably an oxide layer) 10 is formed over asubstrate 8, for example, a semiconductor substrate. The oxide layer 10is preferably comprised of silicon oxide, but could be comprised ofother well known oxide materials such as silicon dioxide, aluminumoxide, or tetraethylorthosilicate (TEOS). For simplicity of description,the substrate 8 is omitted in FIGS. 3-17.

With reference to FIG. 3, a trench 12 is etched into the oxide layer 10by chemical etching, reactive ion etching (RIE), or other means ofcreating a trench in the oxide layer 10. The trench 12 creates an oxidelayer 10 having a first upper level 13 and second lower level 15, bothfirst and second levels connected by a sidewall region 11.

In FIG. 4, a liner 14 is deposited on the silicon oxide layer 10. Theliner 14 can be formed of a material selected from the group including,but not limited to, tantalum (Ta), titanium (Ti), titanium-tungsten(TiW), titanium-nitride (TiN), tungsten-silicide (WSi₂),tungsten-nitride (WN), or chromium (Cr). The liner 14 is optional, butpreferred because it serves as an adhesion layer for a later formedferromagnetic cladding layer 16 (FIG. 5).

It should be noted that trench 12 may optionally be filled with materialused to form the liner 14, or any other subsequent layer, and then,through etching or abrasion of the structure, the trench 12 could beredefined. This ensures that each subsequent layer is formed within thetrench 12.

As depicted in FIG. 5, a ferromagnetic cladding layer 16 is depositedover the liner 14. The ferromagnetic cladding layer 16 can be formedfrom a variety of materials, including, but not limited to, nickel-iron(Ni—Fe), cobalt-iron (Co—Fe), cobalt-nickel-iron (Co—Ni—Fe), iron (Fe),nickel (Ni), cobalt (Co), or other highly permeable materials. Theferromagnetic cladding layer 16 provides a closed magnetic path (fluxclosure) around a subsequently formed write conductor 20 (FIG. 7). Theferromagnetic cladding layer 16 also substantially attenuates fringemagnetic fields that can interfere or corrupt bit information stored inthe MTJ elements of neighboring memory cells.

Referring to FIG. 6, a barrier layer 18 is provided over theferromagnetic cladding layer 16. The barrier layer 18 may be formed of aconventional insulator, for example, a low pressure chemical vapordeposition (CVD) oxide, a nitride, such as Si₃N₄, low pressure or highpressure TEOS, or boro-phospho-silicate glass (BPSG). The barrier layer18 is an optional layer, and is preferable if the resistance of thecladding material used to form the ferromagnetic cladding layer 16 isgreater than {fraction (1/10)} the resistance of the conductor materialused to form the write conductor 20 (FIG. 7). The barrier layer 18 isalso preferable if the cladding material used to form the ferromagneticcladding layer 16 is not fully removed from the regions between thewrite conductor 20 (FIG. 7) and the read conductor 26 (FIG. 11) duringfurther processing. The barrier layer 18 serves as an adhesion layer,and prevents the migration of the conductive material used to form thewrite conductor 20 (FIG. 7) into the lower layers.

It should be noted that if the barrier layer 18 is not formed, a liner17 (FIG. 6A) could be formed over the ferromagnetic cladding layer 16.The liner 17 can be formed of a material selected from the groupincluding, but not limited to, tantalum (Ta), titanium (Ti),titanium-tungsten (TiW), titanium-nitride (TiN), tungsten-silicide(WSi₂), tungsten-nitride (WN), or chromium (Cr). The liner is optional,but preferred in the absence of the barrier layer 18 because it servesas an adhesion layer for the write conductor 20 (FIG. 7).

In FIG. 7, a write conductor 20 is formed over the barrier layer 18. Thewrite conductor 20 is preferably made of copper. It should be noted thatthe write conductor 20 could be made of other conductive materials,including, but not limited to, tungsten, platinum, gold, silver, oraluminum.

In FIG. 8, a second insulating layer 22 is deposited (the oxide layer 10being the first insulating layer). The second insulating layer 22 can beformed of a variety of materials, including, but not limited to, siliconnitrides, alumina oxides, oxides, high temperature polymers, or adielectric material.

In FIG. 9, the layers that have been formed on the first level 13 of theoxide layer 10 are removed, for example, by chemical-mechanicalpolishing (CMP) or RIE dry etching, creating an oxide layer 10 with atrench 12 that has a liner 14, a ferromagnetic cladding layer 16, abarrier layer 18, a write conductor 20, and a second insulating layer22.

Referring to FIG. 10, a third insulating layer 24 is formed over theentire FIG. 9 structure. The third insulating layer 24 is optional.Preferably, a read conductor 26 is formed over the third insulatinglayer 24 and within the trench, as shown in FIG. 11. However, it shouldbe noted that the read conductor 24 could be formed directly over thesecond insulating layer as shown in FIG. 11A. The read conductor 26 ispreferably formed of copper (Cu), but could be made of any otherconductive material, including, but not limited to, tungsten, platinum,gold, silver, tantalum, or aluminum.

The excess material used to form the read conductor 26 is then removedthrough mechanical abrasion, for example, conventional CMP methods,creating a planarized surface in which the topmost surface of the readconductor 26 is planar to the topmost surface of the third insulatinglayer 24 (FIG. 12). Planarizing the structure of FIG. 11A would resultin the structure depicted in FIG. 12A, specifically, a topmost surfaceof the read conductor 26 is planar to a topmost surface of the secondinsulating layer 22.

Referring to FIGS. 13 and 13A, layers that will form an MTJ element 28are next formed. The MTJ element 28 is formed by three layers, a pinnedmagnetic layer 28 a, a tunnel barrier layer 28 b, and a free magneticlayer 28 c. It should be noted that a variety of other layers could beincluded, but are omitted for purposes of clarity. It should also benoted that the three functional layers could be formed in reverse order.

FIG. 14 depicts the deposition of a hard mask 30. The hard mask 30serves as an etch barrier and protects the underlying MTJ element 28during any further processing. The MTJ element 28 is patterned, oretched, as shown in FIGS. 15 and 15A. In FIGS. 16 and 16A, the hard mask30 is removed, and the resulting structure is an MRAM structure whereinthe read conductor 26 is formed within a recess of the write conductor20. The preceding processes result in a self-aligned, low-resistant, andefficient formation of read and write conductors.

FIG. 17 is a cutaway perspective view of a semiconductor chip 100containing a plurality of MRAM devices 170 manufactured in accordancewith FIGS. 2-16. In accordance with an exemplary embodiment of theinvention, each of a plurality of MRAM devices 170 has a read conductor26 formed in a trench of a write conductor 20. The etching to form theMTJ elements 28 assures discrete MTJ element islands formed over theread conductor 26. A sense line 38 is positioned orthogonally above theMTJ elements 28. The sense line 38 is preferably formed of copper (Cu).It should be noted that the sense line 38 could be made of otherconductive materials, including, but not limited to, tungsten-nitride,tungsten, platinum, gold, silver, or aluminum. The sense line 38 isactivated during a read or write operation. The sense line 38, inconjunction with the read conductor 26 or write conductor 20, selectsthe MTJ element 28 in the array that will either be written to or readfrom.

FIG. 18 illustrates an exemplary processing system 900 utilizing theMRAM memory device as described in connection with FIGS. 2-17. Theprocessing system 900 includes one or more processors 901 coupled to alocal bus 904. A memory controller 902 and a primary bus bridge 903 arealso coupled the local bus 904. The processing system 900 may includemultiple memory controllers 902 and/or multiple primary bus bridges 903.The memory controller 902 and the primary bus bridge 903 may beintegrated as a single device 906.

The memory controller 902 is also coupled to one or more memory buses907. Each memory bus accepts memory components 908 which include atleast one MRAM memory device 170 contains a plurality of MTJ memoryelements formed in accordance with the present invention. The memorycomponents 908 may be a memory card or a memory module. Examples ofmemory modules include single inline memory modules (SIMMs) and dualinline memory modules (DIMMs). The memory components 908 may include oneor more additional devices 909. For example, in a SIMM or DIMM, theadditional device 909 might be a configuration memory, such as a serialpresence detect (SPD) memory. The memory controller 902 may also becoupled to a cache memory 905. The cache memory 905 may be the onlycache memory in the processing system. Alternatively, other devices, forexample, processors 901 may also include cache memories, which may forma cache hierarchy with cache memory 905. If the processing system 900includes peripherals or controllers which are bus masters or whichsupport direct memory access (DMA), the memory controller 902 mayimplement a cache coherency protocol. If the memory controller 902 iscoupled to a plurality of memory buses 907, each memory bus 907 may beoperated in parallel, or different address ranges may be mapped todifferent memory buses 907.

The primary bus bridge 903 is coupled to at least one peripheral bus910. Various devices, such as peripherals or additional bus bridges maybe coupled to the peripheral bus 910. These devices may include astorage controller 911, a miscellaneous I/O device 914, a secondary busbridge 915, a multimedia processor 918, and a legacy device interface920. The primary bus bridge 903 may also be coupled to one or morespecial purpose high speed ports 922. In a personal computer, forexample, the special purpose port might be the Accelerated Graphics Port(AGP), used to couple a high performance video card to the processingsystem 900.

The storage controller 911 couples one or more storage devices 913, viaa storage bus 912, to the peripheral bus 910. For example, the storagecontroller 911 may be a SCSI controller and storage devices 913 may beSCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be a local area network interface, suchas an Ethernet card. The secondary bus bridge may be used to interfaceadditional devices via another bus to the processing system. Forexample, the secondary bus bridge may be a universal serial port (USB)controller used to couple USB devices 917 via to the processing system900. The multimedia processor 918 may be a sound card, a video capturecard, or any other type of media interface, which may also be coupled toone additional device such as speakers 919. The legacy device interface920 is used to couple legacy devices, for example, older styledkeyboards and mice, to the processing system 900.

The processing system 900 illustrated in FIG. 18 is only an exemplaryprocessing system with which the invention may be used. While FIG. 18illustrates a processing architecture especially suitable for a generalpurpose computer, such as a personal computer or a workstation, itshould be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908 and/or memorydevices 170. These electronic devices may include, but are not limitedto audio/video processors and recorders, gaming consoles, digitaltelevision sets, wired or wireless telephones, navigation devices(including system based on the global positioning system (GPS) and/orinertial navigation), and digital cameras and/or recorders. Themodifications may include, for example, elimination of unnecessarycomponents, addition of specialized devices or circuits, and/orintegration of a plurality of devices.

The above description and accompanying drawings are only illustrative ofexemplary embodiments, which can achieve the features and advantages ofthe present invention. It is not intended that the invention be limitedto the embodiments shown and described in detail herein. The inventioncan be modified to incorporate any number of variations, alterations,substitutions or equivalent arrangements not heretofore described, butwhich are commensurate with the spirit and scope of the invention.Accordingly, the invention is not limited by the foregoing description,but rather is limited only by the scope of the appended claims.

1-95. (canceled)
 96. A method of forming a memory array structure, themethod comprising: forming a plurality of memory cell structures, eachof said memory cell structures formed by the steps of; forming a trenchin a first insulating layer to define first and second levels, saidfirst and second levels connected by at least a sidewall region, forminga ferromagnetic cladding layer within said trench and over said secondlevel and said sidewall region of said first insulating layer, forming afirst conductive layer within said trench and over a second level and asidewall region of said ferromagnetic cladding layer, forming a secondinsulating layer within said trench and over a second level and asidewall region of said first conductive layer, forming a secondconductive layer within said trench, and forming a magnetic tunneljunction element over said second conductive layer.
 97. The method ofclaim 96 further comprising said first insulating layer formed over asemiconductor substrate, said semiconductor substrate being formed of amaterial selected from the group consisting of silicon,silicon-on-insulator, silicon-on-sapphire, silicon-germanium, germanium,or gallium arsenide.
 98. The method of claim 96, wherein said firstconductive layer is a write conductor, and said second conductive layeris a read conductor.
 99. The method of claim 96, wherein said firstinsulating layer is formed of a material selected from the groupconsisting of silicon oxide, silicon dioxide, aluminum oxide, andtetraethylorthosilicate.
 100. The method of claim 96, wherein saidferromagnetic cladding layer is formed of a material selected from thegroup consisting of nickel-iron, cobalt-iron, cobalt-nickel-iron, iron,nickel, and cobalt.
 101. The method of claim 96, wherein said first andsecond conductive layers are formed of a material selected from thegroup consisting of tungsten, platinum, gold, silver, aluminum, andcopper.
 102. The method of claim 96, wherein said second insulatinglayer is formed of a material selected form the group consisting ofsilicon nitride, alumina oxides, and oxides.
 103. The method of claim96, wherein said second insulating layer is formed of a high temperaturepolymer.
 104. The method of claim 96, wherein said second insulatinglayer is formed of a dielectric material.
 105. The method of claim 96,wherein said act of forming a trench is performed by reactive ionetching.
 106. The method of claim 96, further comprising planarizingsaid second conductive layer, such that a topmost surface of said secondconductive layer is planar to a topmost surface of said first conductivelayer.
 107. The method of claim 106, further comprising planarizing saidsecond conductive layer, such that said topmost surface of said secondconductive layer, and said topmost surface of said first conductivelayer are planar to a topmost surface of said first insulating layer.108. The method of claim 96, further comprising planarizing said firstinsulating layer, said ferromagnetic cladding layer, and said firstconductive layer such that topmost surfaces of each layer are planar toa topmost surface of said second conductive layer.
 109. The method ofclaim 96, further comprising forming a liner between said firstinsulating layer and said ferromagnetic cladding layer.
 110. The methodof claim 109, wherein said liner is formed of a material selected fromthe group consisting of tantalum, titanium, titanium-tungsten, titaniumnitride, tungsten-nitride and chromium.
 111. The method of claim 96further comprising forming a barrier layer between said ferromagneticcladding layer and said first conductive layer.
 112. The method of claim111, wherein said barrier layer is formed of an oxide.
 113. The methodof claim 111, wherein said barrier layer is formed of a low pressurechemical vapor deposition oxide.
 114. The method of claim 111, whereinsaid barrier layer is formed of a nitride.
 115. The method of claim 111,wherein said barrier layer is formed of a low pressure or high pressuretetraethylorthosilicate.
 116. The method of claim 111, wherein saidbarrier layer is formed of boro-phosopho-silicate glass.
 117. The methodof claim 96, further comprising forming a liner between saidferromagnetic cladding layer and said first conductive layer.
 118. Themethod of claim 96, wherein said magnetic tunnel junction elementcomprises: a pinned magnetic layer; a tunnel barrier layer; and a freemagnetic layer.
 119. A memory array structure, comprising: a pluralityof memory cell structures, each of said memory cell structurescomprising; a trench in a first insulating layer defining first andsecond levels, said and second levels being connected by at least asidewall region; a ferromagnetic cladding layer formed within saidtrench and over said second level and said sidewall region of said firstinsulating layer; a first conductive layer formed within said trench andover a second level and a sidewall region of said ferromagnetic claddinglayer; a second insulating layer formed within said trench and over asecond level and a sidewall region of said first conductive layer; asecond conductive layer formed within said trench; and a magnetic tunneljunction element formed over said second conductive layer.
 120. Thememory array structure of claim 119, further comprising said firstinsulating layer formed over a semiconductor substrate.
 121. The memoryarray structure of claim 119, wherein said first conductive layer is awrite conductor, and said second conductive layer is a read conductor.122. The memory array structure of claim 119, wherein said first andsecond conductive layers are formed of a material selected from thegroup consisting of tungsten-nitride, tungsten, platinum, gold, silver,aluminum, and copper.
 123. The memory array structure of claim 119,wherein a topmost surface of said second conductive layer is planar to atopmost surface of said first conductive layer.
 124. The memory arraystructure of claim 119, wherein said topmost surface of said secondconductive layer, and said topmost surface of said first conductivelayer are planar to a topmost surface of said first insulating layer.125. The memory array structure of claim 119, further comprising a linerformed between said first insulating layer and said ferromagneticcladding layer.
 126. The memory array structure of claim 119, furthercomprising a barrier layer formed between said ferromagnetic claddinglayer and said first conductive layer.
 127. The memory array structureof claim 119, further comprising a liner formed between saidferromagnetic cladding layer and said first conductive layer.
 128. Thememory array structure of claim 119, wherein said magnetic tunneljunction element comprises: a pinned magnetic layer; a tunnel barrierlayer; and a free magnetic layer.
 129. A memory device comprising aplurality of magnetoresistive random access memory cell structuresarranged in an array, each of said magnetoresistive random access memorycell structures comprising: a trench in a first insulating layerdefining first and second levels, said and second levels being connectedby at least a sidewall region; a ferromagnetic cladding layer formedwithin said trench and over said second level and said sidewall regionof said first insulating layer; a first conductive layer formed withinsaid trench and over a second level and a sidewall region of saidferromagnetic cladding layer; a second insulating layer formed withinsaid trench and over a second level and a sidewall region of said firstconductive layer; a second conductive layer formed within said trench;and a magnetic tunnel junction element formed over said secondconductive layer.
 130. A memory cell array comprising: a plurality ofmagnetoresistive random access memory cell structures, each of saidmagnetoresistive random access memory cell structures comprising; atrench in a first insulating layer defining first and second levels,said and second levels being connected by at least a sidewall region; aferromagnetic cladding layer formed within said trench and over saidsecond level and said sidewall region of said first insulating layer; afirst conductive layer formed within said trench and over a second leveland a sidewall region of said ferromagnetic cladding layer; a secondinsulating layer formed within said trench and over a second level and asidewall region of said first conductive layer; a second conductivelayer formed within said trench; and a magnetic tunnel junction elementformed over said second conductive layer.